The subject system and method are generally directed to a memory controller for controlling access to a memory device having a three-dimensional stacked (3DS) structure of integrated circuit (IC) chips. The system and method generally provide for assignment of virtual ranks to the chip locations in the memory device, and for conversion of an address defined with reference to a uniform stack configuration to an optimized address defined with reference to a non-uniform stack configuration of the memory device. This results in reduced addressing overhead, among other things.
Memory controllers are well known in the art. They are implemented as digital circuits dedicated to controlling/managing the flow of data written to and read from one or more memory devices. They may be suitably formed as separate devices or integrated with a central processing unit or other main controller, and serve the memory storage and access needs of various control or user application ‘master’ operations processed thereby. Memory controllers implement the logic necessary to read from and write to various types of memory devices, examples of which include dynamic random access memory (DRAM), as well as electrically programmable types of non-volatile memory such as flash memory, and the like.
Memory controllers actuate read and write data operations on the chips within a memory. Recent developments in memory design include the use of three-dimensional stacking (3DS), in which multiple memory chips or devices may be arranged in a “stack” that may be accessed through a point of interface previously configured for accessing a single chip. The resulting 3DS structures provide more data storage and are more flexible in how that storage is arranged.
However, to manage stacked memory, a memory controller must include additional circuitry, not only to select individual chips in a stack, but also to allow for longer memory addresses, and to track a larger number of data storage banks in the coupled memory or memories. That is, the circuitry of a given memory controller may, in practice, place an upper limit on the memory stack size that the memory controller is capable of managing; the size, complexity, and power consumption of a memory controller design may grow exponentially as this limit increases. Such an upper limit in turn places a ceiling on the storage size of 3DS memory.
There is therefore a need to optimize the management of 3DS memory so as to reduce the complexity of a memory controller relative to a maximum stack size of the corresponding memory.